technical summary KS32C6200 microprocessor 2 1. overview samsung ? s KS32C6200 16/32-bit risc micro- controller is designed to provide a cost-effective and high performance micro controller solution for general applications. to reduce total system cost, KS32C6200 also provides 2-ch uart, 2-ch dma, system manager (chip select logic, dram controller), 3-ch timer, parallel port, i/o ports. an outstanding feature of the KS32C6200 is its cpu core, a 16/32-bit risc processor (arm7tdmi) designed by advanced risc machines, ltd. the arm7tdmi core is a low-power, general purpose, microprocessor macro-cell that was developed for use in application-specific and custom-specific integrated circuits. its simple, elegant, and fully static design is particularly suitable for cost-sensitive and power sensitive applications. the KS32C6200 was developed using arm7tdmi core, 0.5um cmos standard cells, and memory compiler. most of the on-chip function blocks were designed using an hdl synthesizer. the KS32C6200 has been fully verified in samsung ? s mcu test environment. the integrated on-chip functions are as follows: static arm7tdmi cpu core 2k byte instruction/data cache system manager (dram control, chip select logic ) 2-ch dma parallel ports (support ieee1284) 2-ch uart 3-ch timer interrupt controller tone generator i/o ports watch dog timer derasterizer 208bit shifter/rotater on-chip debugging support using jtag
technical summary KS32C6200 microprocessor 3 2. features architecture integrated system for general embedded applications, image data processing fully 16/32-bit risc architecture efficient and powerful arm7tdmi cpu core cost-effective jtag-based debug solution system manager 8/16-bit external bus support for rom/sram, dram and external i/o support edo dram programmable access cycle (from 2 to 7 wait cycles) cost-effective memory-to-peripheral interface support self refresh mode. unified instruction/data cache two way set associative cache with 2kbinstructions/data words) lru (least recently used) four depth write buffer uart (sio) two channel uart (serial i/o) with dma based or interrupt based operation; supports 5-bit, 6-bit, 7- bit, or 8-bit serial data transmit/receive programmable baud rate infra-red(ir) tx/rx support(irda) programmable i/o ports 5 programmable i/o ports (giop) 6 input ports (gip) 13 output ports (gop) derasterizer / shifter 16 16 bit rotate by 90/270 degree for raster data rotation reverse 16bit data left/right shift/rotate 7 half words with selectable direction parallel port interface controller dma-based or interrupt-based operation supports ieee standard 1284 communication modes (compatibility mode, nibble mode, bytes mode, and ecp mode) supports ecp protocol with or without run-length encoding (rle) automatic handshaking mode for any forward or reverse protocol with software/dma dma (direct memory access) controller 2-channel dmac memory-to-memory,memory-to-parallel port,parallel-to-memory,uart-to-memory, memory-to-uart, i/o-to-memory, memory-to-i/o data transfers without cpu intervention. initiated by software or external dma request. increments or decrements source or 8-bit, 16-bit or 32-bit data transfer timers three programmable 16-bit timers
technical summary KS32C6200 microprocessor 4 tone generator programmable square wave generator watch dog timer 16-bit timer useful for periodic reset or interrupts interrupt controller 15 interrupt sources (external : 2) normal or fast interrupt modes(irq, fiq) operating voltage range 4.75 to 5.25 volt operating frequency up-to 33mhz package type 160-pin tqfp
technical summary KS32C6200 microprocessor 5 block diagram d e r a s t e r i z e r / s h i f t e r c l k g e n . i n t e r r u p t c o n t r o l l e r c n t r d a t a a d d r s y s t e m m a n a g e r t o n e g e n e r a t o r s y s t e m b u s c o n t r o l l e r b u s a r b i t r a t i o n b u s i n t e r f a c e r o m / s r a m / d r a m c o n t r o l l e r b u s r o u t e r i / d c a c h e ( 2 - k b ) c p u ( a r m 7 t d m i ) l b u s w a t c h d o g i / o p o r t s c o n t r o l l e r t i m e r d m a u a r t / s e r i a l i / o p a r a l l e l p o r t i n t e r f a c e a d d r e s s d e c o d e r figure 1. KS32C6200 block diagram
technical summary KS32C6200 microprocessor 6 pin assignments k s 3 2 c 6 2 0 0 1 6 0 t q f p ( t o p v i e w ) n c n c n c n c n c n c n c n c n c n c g n d 1 n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c n c v c c 1 g n d 2 g o p 1 2 n c n c n c n c n c n c g p i o 0 / t c k g p i o 1 / t m s g p i o 2 / t d i g p i o 3 / n t r s t g p i o 4 / t d o v c c 2 n f a u l t p e r r o r b u s y n a c k s e l e c t n i n i t n s l c t i n n a u t o f d n s t r o b e g n d 3 p p d 7 p p d 6 p p d 5 p p d 4 p p d 3 p p d 2 p p d 1 p p d 0 2 4 5 c l k v c c 3 d a t a 0 d a t a 1 d a t a 2 d a t a 3 d a t a 4 d a t a 5 d a t a 6 g n d 4 d a t a 7 d a t a 8 d a t a 9 d a t a 1 0 d a t a 1 1 d a t a 1 2 d a t a 1 3 d a t a 1 4 d a t a 1 5 v c c 4 n e c s 2 n e c s 1 n e c s 0 v c c 6 n w b e 1 n w b e 0 n w e n o e n c a s 1 n c a s 0 n r a s 1 n r a s 0 n r c s 2 n r c s 1 n r c s 0 g n d 6 a d d r 2 1 a d d r 2 0 a d d r 1 9 a d d r 1 7 a d d r 1 6 a d d r 1 5 a d d r 1 4 v c c 5 a d d r 1 3 a d d r 1 2 a d d r 1 1 a d d r 1 8 a d d r 1 0 a d d r 9 a d d r 8 a d d r 7 a d d r 6 g n d 5 a d d r 5 a d d r 4 a d d r 3 a d d r 2 a d d r 1 a d d r 0 n c v c c 8 g o p 7 / n i o r d 1 g o p 6 / n i o w r 2 g o p 1 1 g o p 1 0 / f i r e p u l s e g o p 9 / c l k o u t g o p 8 / n i o r d 2 g o p 4 / n r s t o g o p 3 / t o n e g n d 9 e e c l k e e d a t a n c n c n c n c n c n c g o p 2 / n x d a c k g i p 4 / n x d r e q g i p 3 / n e i n t 2 g i p 2 / n e i n t 1 v c c 7 g o p 5 / n i o w r 1 g n d 8 m c l k n r e s e t g n d 7 c l k s e l g i p 5 / u c l k t e s t 2 t e s t 1 g i p 1 / r x d 2 g o p 1 / t x d 2 g i p 0 / r x d 1 g o p 0 / t x d 1 n e c s 3 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 1 6 0 1 5 9 1 5 8 1 5 7 1 5 6 1 5 5 1 5 4 1 5 3 1 5 2 1 5 1 1 5 0 1 4 9 1 4 8 1 4 7 1 4 6 1 4 5 1 4 4 1 4 3 1 4 2 1 4 1 1 4 0 1 3 9 1 3 8 1 3 7 1 3 6 1 3 5 1 3 4 1 3 3 1 3 2 1 3 1 1 3 0 1 2 9 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 0 8 1 0 7 1 0 6 1 0 5 1 0 4 1 0 3 1 0 2 1 0 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 n c n c n o t e ; ' n c ' p i n s a r e r e s e r v e d f o r a d d i t i o n a l f u n c t i o n u n i t s n o c o n n e c t i o n i s r e c o m m e n d e d figure 2. KS32C6200 pin assignments
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